Digital computers have employed control methods and systems for controlling the transfer of digital information between buses and memory and between buses and input/output interfaces.
Computers employing dynamic random access memories ("DRAMs") have used DRAM controllers to provide all the signals necessary to control dynamic memories. DRAM controllers provide, for example, multiplexed addresses and address strobes, refresh logic, and refresh/access arbitration. DRAMs need to be refreshed to avoid loss of data stored in memory.
Computers with two buses have used dual-port DRAM controllers. The Intel Model 8207 Dual-Port DRAM Controller, for example, has a dual-port interface that allows two different buses to independently access memory, and also provides all signals necessary to control certain DRAMs. For both ports of the Model 8207 controller to be operated synchronously the processors used in conjunction with the controller must be the same type (Fast or Slow Cycle) and they must have synchronized clocks. So to run both ports synchronously, the processors must have related timings (both phase and frequency). If these conditions cannot be met, then one port must run synchronous and the other asynchronous.
Operating a prior art DRAM controller asynchronously means that one part of the controller is running at one speed (for example, a slow speed) and the other part is running at a different speed (for example, a fast speed). Operating a prior art DRAM controller asynchronously imposes performance penalties, however. For every handshake involving the controller, the sum of central processing unit ("CPU") synchronizing time and input/output ("I/O") synchronizing time is lost. Said sum of synchronizing times is a relatively large number that is one on the order of a memory access time. Thus, in prior art DRAM controllers, each memory access has associated with it a relatively large amount of time lost in order to achieve synchronization.
Prior art methods of controlling input/output operations for a single bus have also imposed performance limitations. In prior art digital computers, the central processing units ("CPUs") can be slowed down if input/output devices have priority with respect to the use of bus. If the input/output devices do not have priority, then input/output devices can lose data. More networking between computers means more input/output information needs to be processed, which means that CPUs can be slowed down even more. Examples of input/output devices are Ethernet interfaces, disk controllers, and printer interfaces.